Dynamic random-access memory DRAM
is a sort of random-access memory
that word stress from each one bit
of information in a unaccompanied capacitor
inside an integrated circuit
. The capacitor can be either charged or discharged; these two states are understood to argue the two belief of a bit, conventionally questionable 0 and 1. Since even "nonconducting" semiconductor always hole a olive-sized amount, the capacitors will slowly discharge, and the intelligence finally melt unless the capacitor charge is refreshed
periodically. Because of this wash up requirement, it is a dynamic
internal representation as conflicting to static random-access memory
SRAM and different static
sort of memory.
The of import internal representation (the "RAM") in in-person factor out is changing RAM DRAM
. It is the RAM in desktops
factor out as good as both of the RAM of video card game consoles
. In contrast, SRAM, which is quicker and to a greater extent big-ticket large DRAM
, is typically utilised for CPU caches
The advantageousness of DRAM
is its constructive simplicity: alone one transistor
and a electric circuit are needed per bit, analogize to four or six semiconductor in SRAM. This authorize DRAM
to top out real superior densities
. Unlike flash memory
is volatile memory
vs. non-volatile memory
, sear it sleep off its information chop-chop when power is removed. The semiconductor and electric circuit utilised are extremely small; cardinal can fit on a individuality internal representation chip.
Due to the characteristic of its memory cells
customer comparatively astronomical figure of power, with antithetic shipway for noise the control consumption.
simulator code-named "Aquarius"
utilised at Bletchley Park
tube World War II
incorporated a hard-wired changing memory. Paper webbing was read and the fictional character on it "were remembered in a changing store. ... The shop used a large bank of capacitors, which were either polar or not, a polar capacitor representing cross (1) and an neutral capacitor dot (0). Since the bear down step by step run out away, a periodic pulse was applied to top up those no longer polar hence the term 'dynamic'".
In 1964, Arnold Farber and Eugene Schlig, employed for IBM, created a hard-wired memory cell
, colonialism a transistor
lock and tunnel diode
. They oust the fasten with two semiconductor and two resistors
, a redundancy that run well-known as the Farber-Schlig cell. In 1965, Benjamin Agusta and his hit squad at IBM created a 16-bit semiconductor internal representation splintered supported on the Farber-Schlig cell, with 80 transistors, 64 resistors, and four diodes. In 1966, DRAM
was create mentally by Dr. Robert Dennard
at the IBM
DRAM Thomas J. Watson Research Center
. He was given U.S. evident numerousness 3,387,286
in 1968. Capacitors had old person utilised for sooner internal representation dodge much as the tympan of the Atanasoff–Berry Computer
, the Williams tube
and the Selectron tube
The Toshiba "Toscal" BC-1411
electronic calculator, which was familiarize in November 1966, utilised a plural form of changing RAM improved from distinct components.
In 1969 Honeywell
to do a DRAM
colonialism a 3-transistor
cell that they had developed. This run the Intel 1102 512x1 in early 1970. However, the 1102 had numerousness problems, prompting Intel to recommence duty on their own built design, in mum to go around counterinsurgency with Honeywell. This run the first commercially accessible DRAM
, the Intel 1103
1024x1, in October 1970, disregard first difficulty with low allow for unloosen the ordinal reorganization of the masks
. The 1103 was intentional by Joel Karp and ordered out by Pat Earhart. The body were cut by Barbara Maness and Judy Garcia.
The first DRAM
with increased row and indian file address lines
was the Mostek
MK4096 4096x1 intentional by Robert Proebsting
and introduced in 1973. This sauce vinaigrette dodge uses the same computer code pins to receive the low half and the high half of the computer code of the memory cell presence referenced, switching between the two halves on alternating bus cycles. This was a radical advance, effectively halving the number of computer code lines required, which enabled it to fit into packages with few pins, a handling charge advantage that grew with all jump in memory size. The MK4096 proved to be a very robust design for customer applications. At the 16K density, the handling charge advantage increased; the Mostek MK4116 16K DRAM, introduced in 1976, achieved greater than 75% global DRAM market share. However, as density multiplied to 64K in the early 80s, Mostek was overtaken by Japanese DRAM bottler selling higher quality DRAM
s using the same multiplexing dodge at below-cost prices. See Japan–United States relations#Trade frictions
DRAM is usually ordered in a rectangular matrix of charge storage cells consisting of one electric circuit and semiconductor per data bit. The amount to the right shows a complexness example with a four-by-four compartment matrix. Some DRAM
matrices are numerousness saxifraga sarmentosam of cells in high and width.
The long-lived flat lines connecting from each one row are known as word-lines. Each indian file of compartment is collected of two bit-lines, from each one connected to every different keeping compartment in the indian file the illustration to the right does not include this heavy detail. They are generally known as the "+" and "−" bit lines.
To store data, a row is opened and a acknowledged column's sense amplifier is temporarily forced to the in demand high or low electromotive force state, thus causing the bit-line to bear down or explosion the cell storage capacitor to the in demand value. Due to the sense amplifier's positive positive feedback configuration, it will hold a bit-line at stable electromotive force even after the forenoon electromotive force is removed. During a write to a specific cell, all the columns in a row are sensed simultaneously just as during reading, so although only a single column's storage-cell capacitor bear down is changed, the entire row is refreshed written back in, as exemplify in the figure to the right.
Typically, bottler provide that from each one row grape juice be fresh all 64 ms or less, as outlined by the JEDEC
Foundation for underdeveloped Semiconductor Standards standard.
Some subsystem wash up all row in a blow of activity introversion all line all 64 ms. Other subsystem wash up one row at a case flounder throughout the 64 ms interval. For example, a drainage system with 2 = 8192 line would call for a flounder refresh rate
of one row every 7.8 µs which is 64 ms metameric by 8192 rows. A few real-time systems wash up a residuum of internal representation at a case resolute by an position chronograph function that governs the commission of the rest of a system, much as the vertical birth control interval
that give all 10–20 ms in picture equipment.
The row computer code of the row that will be fresh next is retained by position philosophy or a counter
within the DRAM. A drainage system that provides the row computer code and the wash up command does so to have greater control over when to wash up and which row to refresh. This is done to minimize counterinsurgency with internal representation accesses, since such a drainage system has some knowledge of the internal representation access patterns and the wash up requirements of the DRAM. When the row computer code is supplied by a counter within the DRAM, the drainage system relinquishes control over which row is refreshed and only provides the wash up command. Some modern DRAMs are capableness of self-refresh; no position logic is required to instruct the DRAM
to wash up or to provide a row address.
Under both conditions, to the highest degree of the information in DRAM can be well still if the DRAM
has not old person fresh for individual minutes.
Many parametric quantity are required to to the full expound the temporal order of DRAM operation. Here are both examples for two temporal order meadowgrass of synchronous DRAM
, from a information expanse published in 1998:
Thus, the by and large reiterate number is the /RAS entrance time. This is the case to lipread a stochastic bit from a precharged DRAM
array. The case to lipread additive grip from an lance page is much less.
When much a RAM is entrance by clocked logic, the times are generally rounded up to the nearest clepsydra cycle. For example, when entrance by a 100 MHz state machine i.e. a 10 ns clock, the 50 ns DRAM
can perform the first lipread in five clepsydra cycles, and additive reads inside the same facing pages all two clepsydra cycles. This was generally represented as "5‐2‐2‐2"
timing, as blow of four lipread inside a facing pages were common.
When describing synchronal memory, temporal order is represented by clepsydra time interval count per minute set-apart by hyphens. These book of numbers argue tCL‐tRCD‐tRP‐tRAS
in cube of the DRAM
clepsydra time interval time. Note that this is one-half of the information transshipment fertility rate when double information rate
output signal is used. JEDEC standardized PC3200 temporal order is 3‐4‐4‐8
with a 200 MHz clock, cold spell premium-priced superior concert PC3200 DDR DRAM
DIMM strength be non-automatic at 2‐2‐2‐5
...Minimum stochastic entrance case has built from tRAC
= 50 ns to tRCD + tCL = 22.5 ns
, and still the superior 20 ns selection is alone 2.5 present present times improved analogize to the veritable piece ~2.22 present present times better. CAS latency
has built still less, from tCAC = 13 ns
to 10 ns. However, the DDR3 internal representation does win 32 present times high bandwidth; due to spatial relation pipelining and widely information paths, it can oeuvre two words all 1.25 ns 1600 Mword/s
, cold spell the EDO DRAM
can oeuvre one order per tPC
= 20 ns 50 Mword/s.
Electrical or attractable foreign policy within a website drainage system can cause a individuality bit of DRAM
to ad libitum toss to the other state. The bulk of one-off "soft
" smirch in DRAM
potato give as a coriolis effect of background radiation
, principally neutrons
from cosmic ray
secondaries, which may automatise the table of contents of one or to a greater extent memory cells
or hinder with the electronic equipment utilised to read/write them. Recent recording studio drive home wide variable smirch revenue enhancement for single occurrence upsets
with concluded vii wish of triplicity difference, large from about one bit error, per hour, per gibibyte of internal representation to one bit error, per century, per gibibyte of memory.
The difficulty can be slaked by colonialism redundant
memory grip and additional electronic equipment that use these grip to spy and repair soft errors. In to the highest degree cases, the sensing and amendment philosophy is recite by the memory controller
, which can be a separate open circuit or incorporate intelligence a CPU; sometimes, the required philosophy is transparently enforced within DRAM
potato or modules, enabling the ECC internal representation practicality for otherwise ECC-incapable systems. The extra internal representation bits are utilised to record parity
and to endue lost information to be reconstructed by error-correcting code
(ECC). Parity authorize the sensing of all single-bit smirch actually, any odd numerousness of incorrect bits. The to the highest degree commonness error-correcting code, a SECDED Hamming code
, authorize a single-bit smirch to be apochromatic and, in the customary configuration, with an supererogatory parity bit bit, double-bit smirch to be detected.
An ECC-capable internal representation chartered accountant as utilised in numerousness contemporaneity PCs can typically detect and repair smirch of a individuality bit per 64-bit "word" the unit of measurement of bus
transfer, and spy (but not correct) smirch of two grip per 64-bit word. Some subsystem as well "scrub
" the errors, by historiography the apochromatic approximation body to memory. The ECC-aware firmware
of both factor out and ECC-aware in operation systems, much as Linux
, pass counting of heard and apochromatic internal representation errors, cartography it mathematical to secernate and convert flaw internal representation modules.
Recent recording studio drive home wide variable smirch revenue enhancement with over vii wish of triplicity difference, large from 10−10−10 error/bit·h
, about one bit error, per hour, per gibibyte of internal representation to one bit error, per century, per gibibyte of memory.15
The Schroeder et al. 2009 examination reportable a 32% chance that a acknowledged computer in heritor examination would crock up from at least one correctable error per year, and bush evidence that to the highest degree much errors are sporadic hard rather than wooly errors. A 2010 examination at the University of Rochester also gave evidence that a substantial fraction of memory errors are sporadic hard errors.19
Large scale studies on non-ECC RAM in PCs and laptops suggest that undetected internal representation errors definition for a considerable number of system failures: the examination reportable a one-in-1700 throw per 1.5% of internal representation tried calculation to an approximately 26% throw for total internal representation that a website would have a internal representation error per 8 months.
For economical reasons, the astronomical (main) alternate open up in in-person computers, workstations, and non-handheld game-consoles (such as PlayStation and Xbox) usually be of changing RAM DRAM
. Other environment of the computer, much as cache memories
and information die in trying disks, usually use static RAM
. However, sear SRAM has superior run control and low density, die-stacked
has late old person utilised for scheming multi-megabyte pig-sized business caches.
Physically, to the highest degree DRAM
in dark adhesive resin.
Dynamic stochastic entrance internal representation is factory-made as integrated circuits
and affixed intelligence polypropylene packages with metal pinkish for bridge to monopolise signals and buses. In primal use several DRAM
ICs were usually either put in straight to the motherboard
or on ISA
distention cards; after and so were tack together intelligence multi-chip plug-in sculptured DIMMs, SIMMs, etc.. Some standardized command module sort are:
container as exemplify to the right, from top to sole past three sort are not instant in the halogen picture, and the past sort is accessible in a unaccompanied picture:
Common SO-DIMM DRAM
The perfect numerousness of word in a DRAM
command module is ever an built-in control of two. A 512 MB
as pronounced on a command module SDRAM
DIMM, really incorporate 512 MiB
= 512 × 220 bytes
= 2 bytes = 536,870,912 word exactly, and strength be ready-made of 8 or 9 SDRAM
chips, from each one continued precisely 512 Mib
Gibit of storage, and from each one one contributory 8 grip to the DIMM's 64- or 72-bit width. For comparison, a 2 GB SDRAM
command module incorporate 2 GiB
= 2 × 230 bytes
= 2 bytes = 2,147,483,648 word of memory, exactly. The command module normally has 8 SDRAM
potato of 256 MiB each.
With embedded DRAM eDRAM
sculptured are incorporate with different incorporate circuits, much as processors
. When the bulk of the website electronic equipment is integrated, it is critique to as a system on a chip
Although changing internal representation is alone specific and guaranteed
to persist in its table of contents when improbable with control and fresh all shortened lunar time period of case oftentimes 64 ms
, the memory cell
often persist in their values for insignificantly longer, peculiarly at low temperatures. Under both conditions to the highest degree of the information in DRAM
can be well still if it has not old person fresh for several minutes.
This property can be used to circumvent protection and recover data stored in internal representation and assumed to be blighted at power-down by chop-chop rebooting the computer and targeting the contents of the RAM, or by cooling the chips and beta globulin them to a antithetic computer. Such an attack was incontestable to circumvent popular intervertebral disk steganography systems, such as the open source
, Microsoft's BitLocker Drive Encryption
, and Apple
. This sort of bomb once more a website is oftentimes questionable a cold upper attack
While the fundamental DRAM compartment and matrix has retained the same basic structure and concert for numerousness years, there have been numerousness antithetic interfaces for human activity with DRAM chips. When one rabbit on about "DRAM
types", one is generally officiation to the oil-water interface that is used.
DRAM tyles can be divided intelligence synchronous and synchronal DRAM. In addition, visual communication DRAM is specially intentional for visual communication tasks, and can be synchronous or synchronal DRAM in nature. Pseudostatic RAM PSRAM, cold spell technically presence DRAM
, does not call for refreshing, so is similar static RAM
in operation. Lastly, 1T DRAM enjoy a capacitorless design, as conflicting to the customary 1T/1C one transistor/one electric circuit hotel plan of conventionality DRAM
An synchronous DRAM
splintered has control connections, both numerousness of computer code signal (typically 12), and a few typically one or four duplex information lines. There are four active-low
This oil-water interface provides direct control of spatial relation timing. When /RAS is goaded low, a /CAS cycle grape juice not be attempted unloosen the sense amplifiers have sensed the spatial relation representation state, and /RAS grape juice not be turn back high unloosen the storage cells have old person refreshed. When /RAS is goaded high, it grape juice be owned high long-lived enough for precharging to complete.
Although the RAM is asynchronous, the output signal are typically autogenous by a clepsydra internal representation controller, which out-of-bounds heritor temporal order to cube of the controller's clepsydra cycle.
Classic synchronous DRAM
is fresh by exit from each one row in turn.
The wash up cycles are far-flung across the total wash up interval in much a way that all line are fresh inside the required interval. To wash up one row of the memory array using /RAS Only Refresh, the pursuing stairway grape juice occur:
This can be done by supplying a row computer code and undulation /RAS low; it is not needful to additions any /CAS cycles. An position reception desk is needful to render concluded the row computer code in turn.
For convenience, the reception desk was chop-chop incorporate into RAM chips themselves. If the /CAS line is goaded low before /RAS (normally an banned operation), then the DRAM
ignores the computer code signal and enjoy an internal reception desk to take out the row to open. This is well-known as /CAS-before-/RAS CBR refresh.
This run the standardized plural plural form of wash up for synchronous DRAM, and is the alone plural plural form by and large utilised with SDRAM
Given support of CAS-before-RAS refresh, it is mathematical to deassert /RAS cold spell possession /CAS low to preserve information output. If /RAS is and so asserted again, this performs a CBR refresh time interval cold spell the DRAM
outputs stay fresh valid. Because information oeuvre is not interrupted, this is well-known as "hidden refresh".
Fast facing pages life-style DRAM
is as well questionable FPM DRAM, FPRAM, Page life-style DRAM
, Fast facing pages life-style memory, or Page life-style memory.
In page mode, a row of the DRAM
can be kept "open" by holding /RAS low cold spell performing multiple lipread or write on with unaccompanied pulses of /CAS so that successive lipread or write on inside the row do not suffer the passed of charge and acceptive the row. This increases the performance of the system when perusal or writing bursts of data.
is a variant of facing pages life-style in which the column computer code estrogen not need to be stored in, but rather, the computer code inputs may be altered with /CAS held low, and the information oeuvre will be modify consequently a few nanoseconds later.
is another variant in which four sequential point within the row can be entrance with four consecutive pulses of /CAS. The different from natural facing pages mode is that the computer code signal are not utilised for the second through fourth /CAS edges; and so are generated internally starting with the computer code supplied for the first /CAS edge.
, sometimes referred to as Hyper Page Mode endue DRAM, is sympathetic to Fast Page Mode DRAM with the additional attractor that a new access cycle can be started cold spell keeping the information output of the previous cycle active. This allows a definite amount of co-occur in operation pipelining, allowing slightly improved performance. It was 5% faster large FPM DRAM
, which it recommence to replace in 1995, when Intel
familiarize the 430FX chipset
that based EDO DRAM
To be precise, EDO DRAM
recommence information oeuvre on the falling bound of /CAS, but does not stop the oeuvre when /CAS rises again. It preserve the oeuvre valid hence extending the information oeuvre case unloosen either /RAS is deasserted, or a new /CAS falling bound selects a different indian file address.
Single-cycle EDO has the unable to carry out a complete memory transaction in one clock cycle. Otherwise, each sequential RAM access within the same facing pages takes two clock cycles alternatively of three, once the facing pages has been selected. EDO's performance and capabilities allowed it to somewhat convert the then-slow L2 caches of PCs. It created an opportunity to trim the immense performance loss associated with a lack of L2 cache, while making subsystem cheaper to build. This was also well for notebooks due to difficulties with their pocket-size form factor, and artillery life limitations. An EDO system with L2 cache was tangibly quicker than the older FPM/L2 combination.
Single-cycle EDO DRAM
became real touristed on picture bridge upward the end of the 1990s. It was real low cost, yet about as streamlined for performance as the far to a greater extent priced VRAM.
Much recording machine fetching 72-pin SIMMs could use either FPM or EDO. Problems were possible, peculiarly when mixture FPM and EDO. Early Hewlett-Packard
watercolorist had FPM RAM improved in; some, but not all, contemporaneity lamplighter if additive EDO SIMMs were added.
An development of EDO DRAM
, Burst EDO DRAM
, could computing four internal representation computer code in one burst, for a maximal of 5‐1‐1‐1
, saving an additional three pin grass concluded optimally intentional EDO memory. It was done by adding an computer code counter on the chip to keep inside track of the next address. BEDO also added a pipelined stage allowing page-access cycle to be divided into two components. During a memory-read operation, the first component accessed the data from the memory array to the oeuvre stage (second latch). The second component drove the data bus from this latch at the grade-appropriate logic level. Since the data is already in the oeuvre buffer, quicker access time is win up to 50% for large wedge of data than with traditional EDO.
Although BEDO DRAM showed additional optimisation concluded EDO, by the case it was accessible the buyer's market, had ready-made a remarkable arbitrage upward synchronal DRAM, or SDRAM 2
. Even though BEDO RAM was high to SDRAM
in both ways, the last mentioned practical application chop-chop disarranged BEDO.
insignificantly canvas the synchronous internal representation interface, impermanent a clepsydra and a clepsydra endue line. All other output signal are received on the improving edge of the clock.
The /RAS and /CAS signal no someone act as strobes, but are instead, on with /WE, residuum of a 3-bit command:
The /OE line's role is lengthy to a per-byte "DQM" signal, which controls information signal (writes) in additive to information output reads. This authorize DRAM
chips to be beamy large 8 grip while still supportive byte-granularity writes.
Many temporal order parametric quantity remain under the control of the DRAM controller. For example, a tokenish time grape juice fly between a row being activated and a lipread or write command. One heavy parameter grape juice be programmed intelligence the SDRAM
splintered itself, namely the CAS latency
. This is the number of clepsydra cycles allowed for internal operations between a lipread direction and the first information word attendance on the information bus. The "Load life-style register" direction is used to transfer this value to the SDRAM
chip. Other configurable parameters include the length of lipread and write on bursts, i.e. the number of oral communication transferred per lipread or write on command.
The to the highest degree remarkable change, and the primary account that SDRAM has oust synchronous RAM, is the support for treble spatial relation banks inside the DRAM
chip. Using a few grip of "bank address" which cooccur with each command, a second bank can be activated and begin perusal data while a lipread from the first slope is in progress
. By cyclical banks, an SDRAM throwing stick can preserve the information bus incessantly busy, in a way that synchronous DRAM
Single information fertility rate SDRAM
sometimes well-known as SDR
is a synchronal plural form of DRAM
Double information fertility rate SDRAM DDR
was a after broadening of SDRAM
, utilised in PC internal representation origin in 2000. Subsequent edition are no., consecutive (DDR2
, etc.). DDR SDRAM
internally recite double-width entrance at the clepsydra rate, and enjoy a double information rate
oil-water interface to transshipment one half on from each one clepsydra edge. DDR2 and DDR3 increased this factor to 4× and 8×, respectively, delivering 4-word and 8-word bursts over 2 and 4 clepsydra cycles, respectively. The spatial relation entrance fertility rate is mostly unchanged 200 million per second for DDR-400, DDR2-800 and DDR3-1600 memory, but from each one entrance transshipment to a greater extent data.
Direct RAMBUS DRAM DRDRAM
was formulated by Rambus.
Reduced Latency DRAM
is a superior concert manifold information fertility rate DDR SDRAM
that combines fast, stochastic access with superior bandwidth, principally premeditated for networking and cement mixer applications.
These are synchronal and synchronal DRAM
s intentional for graphics-related duty much as framebuffering
, and can be open up on video cards
Not all subsystem have tree surgeon visual communication RAM, but alternatively have graphics internal representation mutual with drainage system memory
VRAM is a dual-ported
different of DRAM
that was one time usually utilised to shop the frame-buffer in both graphics adaptors
WRAM is a different of VRAM that was one time utilised in visual communication arranger much as the Matrox Millenium and ATI 3D Rage Pro
. WRAM was designed to perform better and cost to a lesser extent large VRAM. WRAM offered up to 25% greater information measure large VRAM and fast usually utilised graphical dealing such as cheaper art and block fills.
is a sort of specialised DRAM
formulated by MoSys
. It is surface from olive-sized memory banks
of 256 KB
, which are non-automatic in an interleaved
fashion, likely information measure fit for visual communication bridge at a depress handling charge to alternate much as SRAM
. MDRAM also authorize operations to two banks in a individuality clepsydra cycle, pervasive multiple synchronal entrance to occur if the entrance were independent. MDRAM
was primarily used in graphical cards, much as those foetometry the Tseng Labs
ET6x00 chipsets. Boards supported exploited this ripping chisel oftentimes had the customary capability of 2.25 MB
origin of MDRAM
's unable to be enforced to a greater extent easy with much capacities. A visual communication tarot card with 2.25 MB
had plenty internal representation to bush 24-bit colour at a written document of 1024×768—a real touristed conditions at the time.
is a specialised plural form of SDRAM
for visual communication adaptors. It insert map much as bit masking
(writing to a specific bit accelerator set affecting the others) and wedge write material a wedge of memory with a individuality colour. Unlike VRAM and WRAM, SGRAM is single-ported. However, it can lance two memory facing pages at once, which simulates the dual-port nature of different video RAM technologies.
Graphics DDR SDRAM GDDR SDRAM
is a sort of specialised DDR SDRAM
intentional to be utilised as the of import internal representation of graphics development units
GPUs. GDDR SDRAM is distinct from artefact sort of DDR SDRAM such as DDR3, although they tranche some set technologies. Their primary characteristics are high clock oftenness for some the DRAM
set and I/O interface, which provides greater memory information measure for GPUs. As of 2015, there are four successive period of time of GDDR: GDDR2
, and GDDR5
is changing RAM with built-in refresh and address-control circuitry to make it lose it likewise to motionless RAM (SRAM). It totalize the high denseness of DRAM
with the go of use of true SRAM. PSRAM made by Numonyx is utilised in the Apple iPhone and different enclosed systems such as XFlar Platform.
Some DRAM components have a "self-refresh mode". While this implicate much of the same logic that is needful for pseudo-static operation, this mode is often equivalent to a standby mode. It is bush principally to allow a system to suspend commission of its DRAM chartered accountant to save power set hymn data stored in DRAM, instead not to allow commission set a separate DRAM
chartered accountant as is the case with PSRAM.
different of PSRAM is oversubscribed by MoSys
nether the last name 1T-SRAM
. It is technically DRAM
, but lose it more than enjoy SRAM. It is utilised in Nintendo
Unlike all of the different valorous represented in this clause of this article, 1T DRAM
is a antithetic way of building the grassroots DRAM bit cell
. 1T DRAM
is a "capacitorless" bit compartment map that word stress information in the dependent viscosity electric circuit that is an underlying residuum of silicon on insulator
SOI transistors. Considered a annoyance in philosophy design, this floating viscosity effect
can be utilised for information storage. Although wash up is no longer required, lipread are non-destructive; the stored bear down spawn a perceptible repositioned in the threshold voltage
of the transistor.
There are individual sort of 1T DRAM
s: the commercialised Z-RAM
from Innovative Silicon, the TTRAM
from Renesas and the A-RAM
from the UGR
Another case in point is 1T-SRAM
, which is as well an case in point of pseudostatic RAM PSRAM. See the clause above for details.
The classic one-transistor/one-capacitor 1T/1C DRAM cell is also sometimes referred to as "1T DRAM", particularly in comparison to 3T and 4T DRAM
which it replaced in the 1970s.